Dynamic logic gates are widely used in the design of logic circuits which require high performance and minimal size. Dynamic logic gates are much faster than static logic gates, but suffer from increased noise and susceptibility from fabrication process variation. Essentially, a dynamic logic gate is a circuit which requires a periodic electrical pre-charge, or refresh, such as with a dynamic random access memory (DRAM), in order to maintain and properly perform its intended logic function. Once the electrical precharge on the dynamic logic gate has been discharged, the dynamic logic gate can perform no other logic functions until subsequently precharged.
As computer systems have become increasingly faster and substantially smaller in size, techniques have been developed to improve the performance of dynamic logic.
One speed improvement technique is known as a "pipeline" model. A pipelined system utilizes a plurality of dynamic logic circuits arranged in a series of pipeline stages. Each pipeline stage represents the amount of work that can be performed in one clock (i.e., pre-charge) cycle. A pipeline typically utilizes a dual-phase clocking scheme, which is generally implemented using a pair of differential symmetric clocks generated by a centralized clocking circuit. Alternating pipeline stages receive the differential clock signals, CK1 and CK2. Thus, while a given pipeline stage performs an operation during its CK1 enable phase, the immediately subsequent pipeline stage, which depends on the output of the given pipeline stage, waits during its CK2 disable cycle. Then, when CK1 enters the disable cycle, CK2 enters the enable cycle, and the immediately subsequent pipeline stage performs an operation. Pipelining allows operational cycles to be overlapped, and is thus frequently used to increase throughput.
The use of dynamic logic in a pipeline system, however, is problematic. Clock asymmetry results from the use of a dual-phase clocking scheme used in alternating stages of the pipeline to hide the precharge during the "off duty" clock time of a pipeline stage. FIG. 1 graphically illustrates a possible two clock system which may be employed with a pipeline system. In the hypothetical scenario, odd numbered logic stages of N logic stages are clocked by a clock CK1, and even numbered logic stages are clocked by a clock CK2. Clocks CK1 and CK2 are intended by design to switch simultaneously, to be ideally alternating (180 degrees out of phase), and to have a 50 percent duty cycle with respect to one clock state (t.sub.period) of the computer system's clock. However, because of unavoidable clock asymmetry, an "advantaged phase" (t.sub.1 ') and a "disadvantaged phase" (t.sub.2 ') will arise in reality, as comparatively shown in FIG. 1.
Generally, clock asymmetry results from inherent physical inequities in the manufacture of clock generation circuits. A precise time allocation (duty cycle) to the individual pipeline stages can never be achieved. A precise allocation or clocking of time to insure that each pipeline stage of the pipeline has an identical duty cycle is important because it tremendously affects the useful bandwidth of the pipeline, which will be limited to the period of the disadvantaged phase. In other words, the speed of the pipeline is less than optimal because valuable time is wasted in the pipeline stages (either even or odd) operating in the advantaged phase. More time is accorded to the pipeline stages corresponding with the advantaged phase than is necessary for complete operation of the pipeline stages.
Techniques have been developed to compensate for clock asymmetry. U.S. Pat. No. 5,392,423 to Yetter ("Universal Pipeline Latch for Mousetrap Logic Circuits") describes a technique called "phase stealing" whereby pipeline stages (odd or even) which operate in the disadvantaged phase effectively "steal" time from pipeline stages (even or odd) which operate in the advantaged phase. The technique involves the use of a pipeline latch which acts as an edge-triggered latch. The pipeline latch is placed before each pipeline stage, wherein each pipeline stage involves the use of vector logic and mousetrap logic gates. Briefly, vector logic involves the use of a plurality of signals for each data line, permitting more than two valid logic states (i.e., more than the conventional binary "0" and "1") and having one invalid logic state. A mousetrap logic gate comprises an arming mechanism, a functional logic block, and an inverting output buffer. The definition of an invalid state in vector logic allows the functional logic block to accept late inputs. In operation, pre-charging takes place during the pre-charge clock phase. Then, if the vector inputs remain in the invalid state throughout the entire evaluate phase and into the next pre-charge phase, then the pipeline latch at the input of the pipeline stage behaves as an edge-triggered latch for the duration of the pre-charge phase. In other words, a late arriving valid input state will be transferred immediately to the pipeline stage and processed by the pipeline stage. Thus, the pipeline latch allows the vector inputs to be self-timed and phase-stealing from the advantaged phase to be feasible.
The phase-stealing techniques described in U.S. Pat. No. 5,392,423 to Yetter are directed toward taking advantage of clock phase asymmetry in logically balanced alternating pipeline stages. In other words, phase-stealing techniques using a pipeline latch assume balanced clock phases and that the number of logic stages in any two alternating pipeline stages are approximately equal. However, many applications which utilize pipeline techniques require an imbalanced number of logic stages between two alternating pipeline stages. For example, two typical alternating pipeline stages may each require four levels of logic. Because the alternating pipeline stages are balanced in number of logic stages, the pipeline latch phase-stealing technique may be utilized to immunize against phase length asymmetry due to process variations in the actual physical implementation. If, on the other hand, the circuit design calls for six logic stages in one alternating pipeline stage and two logic stages in the other alternating pipeline stage, the pipeline stages are logically imbalanced. With the pipeline latch phase-stealing technique described above, the clock phase would have to be long enough to support the pipeline stage having the greatest number of logic stages, i.e., six levels of logic in this example, resulting in idle time in the alternating pipeline stage having the least number of logic stages, i.e., two levels of logic in this example. A method is needed for artificially inducing clock phase asymmetry to conform to logic asymmetry in alternating pipeline phases.
Another problem suffered by dynamic logic circuits in general, and in the mousetrap logic gates used in the pipeline techniques described above, is the limitation on switching speed caused by inverting output buffer precharge times. One performance improvement technique used to overcome the switching speed problem in inverting output buffers of dynamic logic circuits involves tuning the switching trigger point of a complementary CMOS inverter to the falling input in the forward logic path. This is accomplished with a large ratio of PMOS size to NMOS size (P:N) in the CMOS inverter. Essentially, an imbalanced P:N ratio biases the switching trigger point in one direction or the other. Thus, where the P:N ratio is large (i.e., greater than 1), the complementary CMOS inverter switches more quickly when the inverter input is falling, and more slowly when the inverter input is rising. This standard tuning technique improves the speed of the forward path, but practical considerations such as the required pre-charge time during the off-phase limit the maximum P:N ratio to approximately 4:1. In other words, because the complementary CMOS inverter is tuned to the forward path, the time required to reach the switching trigger point during the pre-charge phase increases. However, the maximum allowable pre-charge time is the time length of the off-phase, and thus the switching trigger point may only be increased to a certain cutoff point without resulting in performance degradation due to not-fully-charged circuit components.
Another problem suffered by dynamic logic circuits is signal degradation on output control lines. This may be the result of a source-destination ground differential. Even where there is a strong drive to ground for control lines that must remain low, a long metal route can induce IR drops. Further, there may be poor power-to-ground strapping between the source and destination, resulting in different source/destination ground potentials. This can affect pass-gate and dynamic logic which may trigger on transistor threshold voltage V.sub.T levels of under 1 volt.
Finally, dynamic logic circuits which have mutually exclusive output control lines, such as differential or vector logic outputs (where only 1 of N lines is high at any given time), often suffer from noise coupling problems and results in output signal degradation.
Accordingly, it would be desirable to provide techniques for enhancing speed in dynamic logic while also improving signal noise immunity and insensitivity to duty cycle variations in the clocks. Specifically, it would be desirable to maximize the effect of phase-stealing in a pipelined system to overcome the logic asymmetry problem in alternating stages of a pipeline latch. In addition, it would be desirable to increase the switching speed of output inverters by increasing the P:N transistor ratio of the CMOS inverter, while removing the dependency of the switching speed from the amount of required pre-charge time in the pre-charge phase. Furthermore, it would be desirable to improve signal quality on output control lines by suppressing high-transitioning pulses on low-driven control lines and also referencing the low control line level to the local ground to immunize pass-gate logic. Finally, it would be desirable to improve output signal quality by preventing coupling between mutually exclusive output control lines.